There is an increasing need for low-voltage, low drop out regulators due to the growing demand in portable electronics, which require low power and low cost system-on-chip designs.
FIG. 1 illustrates a conventional low drop PMOS output regulator 10 that is composed of two gain stages with a negative feedback. The first stage is an error amplifier 12 with a transconductance of gm1. Feedback is provided to the amplifier 12 from a voltage divider with resistors 14 and 16. The amplifier 12 receives the input voltage and a reference voltage Vref on the negative input terminal and the feedback on the positive input terminal. The output stage is a PMOS transistor 18, which has a transconductance of gm2. The output stage of regulator 10 has a common source configuration. The gate of the transistor 18 is coupled to the Vout through a compensation capacitor 20. The load of regulator 10 is illustrated as current source IL, and resistor RL, while capacitor CL is a load capacitor.
In order to obtain enough phase margin for stability of the closed loop transfer function with a constant load, the design should obey the following:
                              1          3                =                                            gm              1                        *                          C              L                                                          gm              2                        *                          C              C                                                          eq        .                                  ⁢        1            where CL is the total load capacitance, and CC is the compensation capacitance from capacitor 20. In order to obtain more phase margin, a series resistor, R>1/gm2, can be inserted between capacitor 20 and the Vout. Such a series resistor results in more closed loop phase margin for better stability.
The design of a regulator 10 that meets equation 1 is not difficult where there is a constant and static current load. Unfortunately, where a variable and dynamic current load is present, regulator 10 is inadequate. Thus, for an on-chip load that generates a very large dynamic spike current, such as that might be found in field programmable gate arrays (FPGAs), the variable dynamic load current will generate a large amount of output voltage noise through the output impedance of the regulator. For example, where the current load is 1.5 A p-p, and the DC impedance of the regulator output is 1 ohm, the resulting noise will be 1.5V p-p, e.g., Vout(noise)=1.5 A p-p*1 ohm=1.5V p-p. If the regulator output is driving a large variable dynamic spike current load, the loop stability through a frequency compensation because particularly difficult to manage.
Accordingly, an improved regulator is needed, particularly for applications that may have dynamic and variable currents, such as in field programmable gate arrays (FPGAs) where the current load depends on the end user's program.